The present invention relates to a semiconductor memory device, and more particularly, to an input/output line precharge circuit, which controls the current (core voltage) for precharge when precharging an input/output line.
In general, a semiconductor memory device, as shown in FIG. 1, includes a write driver 10 which transmits write data DIN through a global input output line pair (GIOT/GIOB) to a main input/output line pair (MIOT/MIOB) at a data input/output pad (DQ PAD) when performing a write operation, and a precharge portion 20 which precharges the main input/output line pair (MIOT/MIOB) with a core voltage VCORE after a write or read operation.
A write driver 10 includes a controller 11 that outputs write control signals WE and WEB using a latch signal YIOW for latching the write data and a signal AYIOS for selecting a data input/output mode, a latch portion 12 that latches the write data DIN inputted by the write control signals WE and WEB, a transmission portion 13 that transmits the latched data, and a driving portion 14 that drives the main input/output line pair (MIOT/MIOB) according to the transmitted data.
The controller 11 comprises a NAND gate (ND1) for NANDing a latch signal YIOW and a data input/output mode selection signal AYIOS, and an inverter (INV1) for inverting a signal outputted from the NAND gate (ND1).
The latch portion 12 comprises an inverter (INV2) that inverts the write data DIN by the write control signals WE and WEB, an inverter (INV3) that inverts the data outputted from the inverter (INV2), and an inverter (INV4) that inverts the data outputted from the inverter (INV3) by the write control signals WE and WEB to provide to an input terminal of the inverter (INV3).
The transmission portion 13 comprises a NAND gate (ND2) that selectively transmits data outputted from the inverter (INV3) according to the write control signal WE, inverters (INV5, INV6) that respectively output a second pull-down signal MIDB and a second pull-up signal MIUB using data transmitted from the NAND gate (ND2), a NAND gate (ND3) that selectively transmits data outputted from the inverter (INV2) according to the write control signal WE, and inverters (INV7, INV8) that respectively output a first pull-down signal MIDT and a first pull-up signal MIUT using data transmitted from the NAND gate (ND3).
The driving portion 14 comprises a PMOS transistor (PM1) that pulls up the main input/output line (MIOT) to a core voltage VCORE by the first pull-up signal MIUT, a NMOS transistor (NM1) that pulls down the main input/output line (MIOT) to a ground voltage VSS by the first pull-down signal MIDT, a PMOS transistor (PM2) that pulls up the main input/output line (MIOB) to the core voltage VCORE by the second pull-up signal MIUB, and a NMOS transistor (NM2) that pulls down the main input/output line (MIOB) to the ground voltage VSS by the second pull-down signal MIDB.
On the other hand, the precharging portion 20 comprises inverters (INV9˜INV11) that invert a precharge signal MIPC with a delay to output to a precharge control signal MIPCB, a PMOS transistor (PM3) that connects the main input/output line pair (MIOT, MIOB) by the precharge control signal MIPCB, and PMOS transistors (PM4, PM5) that precharge the main input/output line pair (MIOT, MIOB) with the core voltage VCORE by the precharge control signal MIPCB.
Looking into an operation of the write driver 10 and the precharge portion 20 in the prior art as described above, first, the main input/output line pair (MIOT, MIOB) is precharged with the core voltage VCORE by the precharge signal MIPC during a precharge operation. When a write operation is initiated, the precharge operation is canceled as the precharge signal MIPC is disabled thereby canceling the precharge operation, and write data DIN is transmitted to the main input/output line pair (MIOT, MIOB). At this time, during the write operation, any one of the main input/output line pair (MIOT, MIOB) is pulled down to the ground voltage VSS, thereby avoiding a degradation of the core voltage VCORE level.
Furthermore, after the write data DIN is transmitted to a bit line pair through the pair of main input/output lines (MIOT, MIOB), the precharge operation is initiated again upon the separation of the bit line pair and the input/output line pair by the column select signal. At this time, there is a problem that current consumption of the core voltage VCORE is generated because the main input/output line pair (MIOT, MIOB) should be precharged again with the core voltage VCORE.
Particularly, when it is in an x16 mode in which data is inputted and outputted in a 16-bit unit, 64 pairs of the main input/output lines (MIOT, MIOB) are precharged for a bank, and therefore, 2 or 4 times of the core voltage VCORE current consumption can be generated compared to an x8 in which data is inputted and outputted in an 8-bit unit, or an x4 in which data is inputted and outputted in a 4-bit unit.
Moreover, when the write operation is performed continuously, the driving capability of the core voltage VCORE driver is unable to follow the operation, and the delay in the response characteristic of the analog VCORE driver generates a severe reduction of the core voltage VCORE during the initial write operation. Accordingly, the above configuration risks the possibility of generating an error during a read operation due to the reduced core voltage VCORE written in the memory cell.